Datasheet

Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695)
Page 672 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
13.2.6 Module Stop Control Register A (MSTPCRA)
7
MSTPA7
0
R/W
Bit
Initial value
R/W
:
:
:
6
MSTPA6
0
R/W
5
MSTPA5
1
R/W
4
MSTPA4
1
R/W
3
MSTPA3
1
R/W
2
MSTPA2
1
R/W
1
MSTPA1
1
R/W
0
MSTPA0
1
R/W
MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPA4 and MSTPA0 bits in MSTPCR is set to 1, the 8-bit timer operation stops at
the end of the bus cycle and a transition is made to module stop mode. For details, see section
24.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset and in software standby mode.
Bit 4—Module Stop (MSTPA4): Specifies the TMR0 and TMR1 module stop mode.
Bit 4
MSTPA4 Description
0 TMR0, TMR1 module stop mode cleared
1 TMR0, TMR1 module stop mode set (Initial value)
Bit 0—Module Stop (MSTPA0): Specifies the TMR2 and TMR3 module stop mode.
Bit 0
MSTPA0 Description
0 TMR2, TMR3 module stop mode cleared
1 TMR2, TMR3 module stop mode set (Initial value)