Datasheet

Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 673 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
13.3 Operation
13.3.1 TCNT Incrementation Timing
TCNT is incremented by input clock pulses (either internal or external).
Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the
system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 13.2 shows the
count timing.
φ
Internal clock
Clock input
to TCNT
TCNT
N–1 N N+1
Figure 13.2 Count Timing for Internal Clock Input
External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in
TCR: at the rising edge, the falling edge, and both rising and falling edges.
Note that the external clock pulse width must be at least 1.5 states for incrementation at a single
edge, and at least 2.5 states for incrementation at both edges. The counter will not increment
correctly if the pulse width is less than these values.
Figure 13.3 shows the timing of incrementation at both edges of an external clock signal.