Datasheet

Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 675 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Timer Output Timing: When compare match A or B occurs, the timer output changes a specified
by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to
0, change to 1, or toggle.
Figure 13.5 shows the timing when the output is set to toggle at compare match A.
φ
Compare match A
signal
Timer output pin
Figure 13.5 Timing of Timer Output
Timing of Compare Match Clear: The timer counter is cleared when compare match A or B
occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.6 shows the
timing of this operation.
φ
N H'00
Compare match
signal
TCNT
Figure 13.6 Timing of Compare Match Clear