Datasheet

Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695)
Page 680 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
13.6 Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit
timer.
13.6.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 13.10 shows this operation.
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N H'00
T1 T2
TCNT write cycle by CPU
Figure 13.10 Contention between TCNT Write and Clear