Datasheet

Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 681 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
13.6.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 13.11 shows this operation.
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
NM
T1 T2
TCNT write cycle by CPU
Counter write data
Figure 13.11 Contention between TCNT Write and Increment