Datasheet

Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695)
Page 682 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
13.6.3 Contention between TCOR Write and Compare Match
During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is disabled even if a compare match event occurs.
Figure 13.12 shows this operation.
φ
Address
TCOR address
Internal write signal
TCNT
TCOR
NM
T1 T2
TCOR write cycle by CPU
TCOR write data
N N+1
Compare match signal
Disabled
Figure 13.12 Contention between TCOR Write and Compare Match