Datasheet

Section 14 14-Bit PWM D/A
(This function is not available in the H8S/2695)
Page 688 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
14.1.2 Block Diagram
Figure 14.1 shows a block diagram of the PWM D/A module.
Internal clock
φ
φ/2
PWM0
PWM1
DADRA
DADRB
DACNT
DACR
Legend:
DACR: PWM D/A control register ( 6 bits)
DADRA: PWM D/A data register A (15 bits)
DADRB: PWM D/A data register B (15 bits)
DACNT: PWM D/A counter (14 bits)
Control logic
Clock selection
Clock
Internal data bus
Basic cycle
compare-match A
Fine-adjustment
pulse addition A
Basic cycle
compare-match B
Fine-adjustment
pulse addition B
Basic cycle overflow
Comparator
A
Comparator
B
Bus interface
Module data bus
Figure 14.1 PWM D/A Block Diagram