Datasheet

Section 14 14-Bit PWM D/A
(This function is not available in the H8S/2695)
Page 690 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
14.2 Register Descriptions
14.2.1 PWM D/A Counter (DACNT)
15
7
0
R/W
14
6
0
R/W
13
5
0
R/W
12
4
0
R/W
11
3
0
R/W
8
0
0
R/W
10
2
0
R/W
9
1
0
R/W
Bit (CPU) :
BIT (Counter)
Initial value :
R/W :
7
8
0
R/W
6
9
0
R/W
5
10
0
R/W
4
11
0
R/W
3
12
0
R/W
0
—
REGS
1
R/W
2
13
0
R/W
1
—
1
—
DACNTH
DACNTL
DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse. The
input clock is selected by the clock select bit (CKS) in DACR. The CPU can read and write the
DACNT value, but since DACNT is a 16-bit register, data transfers between it and the CPU are
performed using a temporary register (TEMP). See section 14.3, Bus Master Interface, for details.
DACNT functions as the time base for both PWM D/A channels. When a channel operates with
14-bit precision, it uses all DACNT bits. When a channel operates with 12-bit precision, it uses the
lower 12 (counter) bits and ignores the upper two (counter) bits.
DACNT is initialized to H'0003 by a reset, in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode, and by the PWME bit.
Bit 1 of DACNTL (CPU) is not used, and is always read as 1.
DACNTL Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS Description
0 DADRA and DADRB can be accessed
1 DACR and DACNT can be accessed (Initial value)