Datasheet

Section 14 14-Bit PWM D/A
(This function is not available in the H8S/2695)
Page 692 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 1—Carrier Frequency Select (CFS)
Bit 1
CFS Description
0 Base cycle = resolution (T) × 64
DADR range = H'0401 to H'FFFD
1 Base cycle = resolution (T) × 256
DADR range = H'0103 to H'FFFF
(Initial value)
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS Description
0 DADRA and DADRB can be accessed
1 DACR and DACNT can be accessed (Initial value)
14.2.3 PWM D/A Control Register (DACR)
7
TEST
0
R/W
6
PWME
0
R/W
5
—
1
—
4
—
1
—
3
OEB
0
R/W
0
CKS
0
R/W
2
OEA
0
R/W
1
OS
0
R/W
Bit :
Initial value :
R/W :
DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and
selects the output phase and operating speed.
DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.