Datasheet

Section 14 14-Bit PWM D/A

(This function is not available in the H8S/2695)

R01UH0166EJ0600 Rev. 6.00 Page 695 of 1434

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Bit 2—Module Stop (MSTPB2): Specifies PWM0 module stop mode.

Bit 2

MSTPB2 Description

0 PWM0 module stop mode is cleared

1 PWM0 module stop mode is set (Initial value)

Bit 1—Module Stop (MSTPB1): Specifies PWM1 module stop mode.

Bit 1

MSTPB1 Description

0 PWM1 module stop mode is cleared

1 PWM1 module stop mode is set (Initial value)

14.3 Bus Master Interface

DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the

on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these

registers, it therefore uses an 8-bit temporary register (TEMP).

These registers are written and read as follows (taking the example of the CPU interface).

• Write

When the upper byte is written, the upper-byte write data is stored in TEMP. Next, when the

lower byte is written, the lower-byte write data and TEMP value are combined, and the

combined 16-bit value is written in the register.

• Read

When the upper byte is read, the upper-byte value is transferred to the CPU and the lower-byte

value is transferred to TEMP. Next, when the lower byte is read, the lower-byte value in

TEMP is transferred to the CPU.

These registers should always be accessed 16 bits at a time (by word access or two consecutive

byte accesses), and the upper byte should always be accessed before the lower byte. Correct data

will not be transferred if only the upper byte or only the lower byte is accessed.

Figure 14.2 shows the data flow for access to DACNT. The other registers are accessed similarly.