Datasheet

Section 14 14-Bit PWM D/A
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 699 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
14.4 Operation
A PWM waveform like the one shown in figure 14.3 is output from the PWMX pin. When OS =
0, the value in DADR corresponds to the total width (T
L
) of the low (0) pulses output in one
conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output
waveform is inverted and the DADR value corresponds to the total width (T
H
) of the high (1)
output pulses. Figure 14.4 shows the types of waveform output available.
t
f
t
L
T
L
= ∑ t
Ln
(when OS = 0)
m
n = 1
1 conversion cycle
(T × 2
14
(= 16384))
Basic cycle
(T × 64 or T × 256)
T: Resolution
(When CFS = 0, m = 256; when CFS = 1, m = 64)
Figure 14.3 PWM D/A Operation
Table 14.4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution,
base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a
certain minimum value. Table 14.4 indicates the range of DADR settings that give an output
waveform like the one in figure 14.3, and lists the conversion cycle length when low-order DADR
bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.