Datasheet

Section 14 14-Bit PWM D/A
(This function is not available in the H8S/2695)
Page 700 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Table 14.4 Settings and Operation (Examples when φ = 10 MHz)
Fixed DADR Bits
Bit Data
CKS
Resolution
T (µs) CFS
Base
Cycle (µs)
Conversion
Cycle (µs)
T
L
(if OS = 0)
T
H
(if OS = 1)
Precision
(Bits)
3 2 1 0
Conversion
Cycle
*
(µs)
0 0.1 0 6.4 1638.4 14 1638.4
12 0 0 409.6
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
10 0 0 0 0 102.4
1 25.6 1638.4 14 1638.4
12 0 0 409.6
1. Always low (or high)
(DADR = H'0003 to
H'00FF)
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
10 0 0 0 0 102.4
1 0.2 0 12.8 3276.8 14 3276.8
12 0 0 819.2
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
10 0 0 0 0 204.8
1 51.2 3276.8 14 3276.8
12 0 0 819.2
1. Always low (or high)
(DADR = H'0003 to
H'00FF)
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
10 0 0 0 0 204.8
Note: * This column indicates the conversion cycle when specific DADR bits are fixed.