Datasheet

Section 14 14-Bit PWM D/A
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 701 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
1. OS = 0 (DADR corresponds to T
L
)
a. CFS = 0 [base cycle = resolution (T) × 64]
t
L1
t
L2
t
L3
t
L255
t
L256
t
f1
t
f2
t
f255
t
f256
1 conversion cycle
t
f1
= t
f2
= t
f3
= · · · = t
f255
= t
f256
= T × 64
t
L1
+ t
L2
+ t
L3
+ · · · + t
L255
+ t
L256
= T
L
Figure 14.4 (1) Output Waveform
b. CFS = 1 [base cycle = resolution (T) × 256]
t
L1
t
L2
t
L3
t
L63
t
L64
t
f1
t
f2
t
f63
t
f64
1 conversion cycle
t
f1
= t
f2
= t
f3
= · · · = t
f63
= t
f64
= T × 256
t
L1
+ t
L2
+ t
L3
+ · · · + t
L63
+ t
L64
= T
L
Figure 14.4 (2) Output Waveform