Datasheet

Section 15 Watchdog Timer
(WDT1 is not available in the H8S/2695)
Page 704 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
15.1.2 Block Diagram
Figure 15.1 (a) and 15.1 (b) show a block diagram of the WDT.
Overflow
Interrupt
control
WOVI 0
(interrupt request
signal)
WDTOVF
Internal reset signal
*
1
Reset
control
RSTCSR TCNT TSCR
φ/2
*
2
φ/64
*
2
φ/128
*
2
φ/512
*
2
φ/2048
*
2
φ/8192
*
2
φ/32768
*
2
φ/131072
*
2
Clock
Clock
select
Internal clock
sources
Bus
interface
Module bus
Legend:
TCSR:
TCNT:
RSTCSR:
Notes:
Timer control/status register
Timer counter
Reset control/status register
Internal bus
WDT
1. The type of internal reset signal depends on a register setting.
There are two alternative types of reset, namely power-on reset and manual reset.
2. The
φ in the subactive and subsleep mode is φSUB.
Figure 15.1 (a) Block Diagram of WDT0