Datasheet

Section 15 Watchdog Timer
(WDT1 is not available in the H8S/2695)
Page 706 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
15.1.3 Pin Configuration
Table 15.1 describes the WDT output pin.
Table 15.1 WDT Pin
Name Symbol I/O Function
Watchdog timer overflow WDTOVF Output Outputs counter overflow signal in watchdog
timer mode
Buzzer output BUZZ
*
Output Outputs clock selected by watchdog timer
(WDT1)
Note: * This function is not available in the H8S/2695.
15.1.4 Register Configuration
Table 15.2 summarizes the WDT register configuration. These registers control clock selection,
WDT mode switching, and the reset signal.
Table 15.2 WDT Registers
Address
*
1
Channel Name Abbreviation R/W Initial Value Write
*
2
Read
0 Timer control/status register 0 TCSR0 R/(W)
*
3
H'18 H'FF74 H'FF74
Timer counter 0 TCNT0 R/W H'00 H'FF74 H'FF75
Reset control/status register RSTCSR R/(W)
*
3
H'1F H'FF76 H'FF77
1 Timer control/status register 1 TCSR1 R/(W)
*
3
H'00 H'FFA2 H'FFA2
Timer counter 1 TCNT1 R/W H'00 H'FFA2 H'FFA3
All Pin function control register PFCR R/W H'0D/H'00 H'FDEB
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 15.2.5, Notes on Register Access.
3. Only a write of 0 is permitted to bit 7, to clear the flag.