Datasheet

Section 15 Watchdog Timer
(WDT1 is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 711 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
WDT0 TCSR Bit 3—Reserved Bit: This bit is always read as 1 and cannot be modified.
WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal
reset request and an NMI request when the TCNT overflows during the watchdog timer mode.
Bit 3
RTS/NMI Description
0 NMI request. (Initial value)
1 Internal reset request.
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (φ) or subclock (φ SUB), for input to TCNT.
Note: In the case of the H8S/2695, only 0 should be written to the RST/NMI bit in the TCSR1
register.
WDT0 Input Clock Select
Description
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0 Clock
*
2
Overflow Period
*
1
(where φ = 25 MHz)
0 0 0 φ/2 (Initial value) 20.4 µs
1 φ/64 655.3 µs
1 0 φ/128 1.3 ms
1 φ/512 5.2 ms
1 0 0 φ/2048 20.9 ms
1 φ/8192 83.8 ms
1 0 φ/32768 335.5 ms
1 φ/131072 1.34 s
Notes: 1. An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the occurrence of a TCNT overflow.
2. In the H8S/2633 Group, the φ in the subactive and subsleep mode is φSUB.