Datasheet

Section 15 Watchdog Timer
(WDT1 is not available in the H8S/2695)
Page 712 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
WDT1
*
1
Input Clock Select
Description
Bit 4
PSS
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0 Clock
Overflow Period
*
2
(where φ = 25 MHz)
(where φ SUB = 32.768 kHz)
0 0 0 0 φ/2 (Initial value) 20.4 µs
1 φ/64 655.3 µs
1 0 φ/128 1.3 ms
1 φ/512 5.2 ms
1 0 0 φ/2048 20.9 ms
1 φ/8192 83.8 ms
1 0 φ/32768 335.5 ms
1 φ/131072 1.34 s
1 0 0 0 φSUB/2 15.6 ms
1 φSUB/4 31.3 ms
1 0 φSUB/8 62.5 ms
1 φSUB/16 125 ms
1 0 0 φSUB/32 250 ms
1 φSUB/64 500 ms
1 0 φSUB/128 1 s
1 φSUB/256 2 s
Notes: 1. WDT1 is not available in the H8S/2695.
2. An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the occurrence of a TCNT overflow.