Datasheet

Section 15 Watchdog Timer
(WDT1 is not available in the H8S/2695)
Page 714 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows
during watchdog timer operation.
For details of the types of reset, see section 4, Exception Handling.
Bit 5
RSTS Description
0 Power-on reset (Initial value)
1 Manual reset
Bits 4 to 0—Reserved: These bits are always read as 1 and cannot be modified.
15.2.4 Pin Function Control Register (PFCR)
7
CSS07
0
R/W
6
CSS36
0
R/W
5
BUZZE
*
0
R/W
4
LCASS
0
R/W
3
AE3
1/0
R/W
0
AE0
1/0
R/W
2
AE2
1/0
R/W
1
AE1
0
R/W
Bit
Initial value
R/W
:
:
:
Note: * This function is not available in the H8S/2695.
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
Only bit 5 is described here. For details of the other bits, see section 7.2.6, Pin Function Control
Register (PFCR).
Bit 5—BUZZ Output Enable (BUZZE): Enables or disables BUZZ output from the PF1 pin.
The WDT1 input clock selected with bits PSS and CKS2 to CKS0 is output as the BUZZ signal.
Bit 5
BUZZE Description
0 Functions as PF1 I/O pin (Initial value)
1 Functions as BUZZ output pin
Note: In the case of the H8S/2695, only 0 should be written to the BUZZ bit.