Datasheet

Section 15 Watchdog Timer

(WDT1 is not available in the H8S/2695)

Page 716 of 1434 R01UH0166EJ0600 Rev. 6.00

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address

H'FF76. It cannot be written to with byte instructions.

Figure 15.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF

bit differs from that for writing to the RSTE and RSTS bits.

To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the

lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write

to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the

write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits,

but has no effect on the WOVF bit.

H'A5 H'00

15 8 7 0

H'5A Write data

15 8 7 0

Writing 0 to WOVF bit

Writing to RSTE and RSTS bits

Address: H'FF76

Figure 15.3 Format of Data Written to RSTCSR (WDT0)

Reading TCNT, TCSR, and RSTCSR (WDT0): These registers are read in the same way as

other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for

RSTCSR.