Datasheet

Section 15 Watchdog Timer
(WDT1 is not available in the H8S/2695)
Page 718 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
TCNT count
H'00
Time
H'FF
WT/IT=1
TME=1
H'00 written
to TCNT
WT/IT=1
TME=1
H'00 written
to TCNT
132 states
*
2
518 states
WDTOVF signal
Internal reset signal
*
1
WT/IT:
TME:
Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1.
2. 130 states when the RSTE bit is cleared to 0.
Overflow
WDTOVF and
internal reset are
generated
WOVF=1
Timer mode select bit
Timer enable bit
Legend:
Figure 15.4 (a) WDT0 Watchdog Timer Operation
TCNT value
H'00
Time
H'FF
WT/IT= 1
TME= 1
Write H'00
to TCNT
WT/IT= 1
TME= 1
Write H'00
to TCNT
515/516 states
Internal
reset signal
WT/IT:
TME:
Overflow
Occurrence
of internal reset
WOVF= 1
*
Timer Mode Select bit
Timer Enable bit
Note:
*
Legend:
The WOVF bit is set to 1 and then cleared to 0 by an internal reset.
Figure 15.4 (b) WDT1 Operation in Watchdog Timer Mode