Datasheet

Section 15 Watchdog Timer
(WDT1 is not available in the H8S/2695)
Page 720 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
φ
TCNT H'FF H'00
Overflow signal
(internal signal)
OVF
Figure 15.6 Timing of Setting of OVF
15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At
the same time, the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR
is set to 1, an internal reset signal is generated for the entire H8S/2633 Group chip. Figure 15.7
shows the timing in this case.
φ
TCNT
H'FF H'00
Overflow signal
(internal signal)
WOVF
WDTOVF signal
Internal reset
signal
132 states
518 states (WDT0)
515/516 states (WDT1)
Figure 15.7 Timing of Setting of WOVF