Datasheet

Section 16 Serial Communication Interface (SCI, IrDA)

(The H8S/2695 is not equipped with an IrDA function)

Page 726 of 1434 R01UH0166EJ0600 Rev. 6.00

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Clocked Synchronous mode

⎯ Serial data communication synchronized with a clock

Serial data communication can be carried out with other chips that have a synchronous

communication function

⎯ One serial data transfer format

Data length: 8 bits

⎯ Receive error detection: Overrun errors detected

• Full-duplex communication capability

⎯ The transmitter and receiver are mutually independent, enabling transmission and reception

to be executed simultaneously

⎯ Double-buffering is used in both the transmitter and the receiver, enabling continuous

transmission and continuous reception of serial data

• Choice of LSB-first or MSB-first transfer

⎯ Can be selected regardless of the communication mode

(except in the case of

asynchronous mode 7-bit data)

Note: * Descriptions in this section refer to LSB-first transfer.

• On-chip baud rate generator allows any bit rate to be selected

• Choice of serial clock source: internal clock from baud rate generator or external clock from

SCK pin

• Four interrupt sources

⎯ Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive

error — that can issue requests independently

⎯ The transmit-data-empty interrupt and receive data full interrupts can activate the DMA

controller (DMAC) or data transfer controller (DTC) to execute data transfer

• Module stop mode can be set

⎯ As the initial setting, SCI operation is halted. Register access is enabled by exiting module

stop mode