Datasheet

Section 16 Serial Communication Interface (SCI, IrDA)
(The H8S/2695 is not equipped with an IrDA function)
Page 752 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Table 16.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)
2 0.3333 333333.3
4 0.6667 666666.7
6 1.0000 1000000.0
8 1.3333 1333333.3
10 1.6667 1666666.7
12 2.0000 2000000.0
14 2.3333 2333333.3
16 2.6667 2666666.7
18 3.0000 3000000.0
20 3.3333 3333333.3
25 4.1667 4166666.7
28 4.6667 4666666.7
16.2.9 Smart Card Mode Register (SCMR)
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
SMIF
0
R/W
2
SINV
0
R/W
1
—
1
—
Bit
Initial value
R/W
:
:
:
SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous
mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication
mode. The descriptions in this chapter refer to LSB-first transfer.
For details of the other bits in SCMR, see section 17.2.1, Smart Card Mode Register (SCMR).
SCMR is initialized to H'F2 by a reset and in standby mode.
Bits 7 to 4—Reserved: These bits are always read as 1 and cannot be modified.