Datasheet

Section 16 Serial Communication Interface (SCI, IrDA)
(The H8S/2695 is not equipped with an IrDA function)
Page 788 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
As per the standard, the High pulse width is a minimum of 1.41 µs, the maximum is (3/16 + 2.5%)
× bit rate, or (3/16 × bit rate) + 1.08 µs. With a 20MHz system clock φ, the minimum High pulse
width can be set to 1.6 µs, which is greater than the 1.41 µs required by the standard.
When the value of the serial data is “1”, no pulse is output.
UART frame
Data
IR frame
Data
0000 011 111
0000 011 111
Start
bit
Transmitting
Receiving
Start
bit
Start
bit
Start
bit
Bit
cycle
Pulse width = 1.6 µs to
3/16ths bit cycle
Figure 16.22 IrDA Transmit and Receive Operations
(2) Receiving
When receiving, the IR frame data is converted into UART frames by the IrDA interface and input
to the SCI.
When a High pulse is detected, “0” is output. If there is no pulse for the duration of 1 bit, “1” is
output. Pulses of less than the minimum pulse width of 1.41 µs are also recognized as “0” data.
(3) Selecting High Pulse Width
Table 16.12 shows the settings of IrCKS2 to IrCKS0 (for the minimum pulse width), at various
LSI operating frequencies, and various bit rates to set the pulse width when transmitting with a
pulse width less than 3/16ths of the bit rate.