Datasheet

Section 1 Overview

Page 32 of 1434 R01UH0166EJ0600 Rev. 6.00

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Type Symbol I/O Name and Function

Clock φ Output System clock: Supplies the system clock to an external

device.

Operating mode

control

MD2 to MD0 Input Mode pins: These pins set the operating mode.

The relation between the settings of pins MD2 to MD0

and the operating mode is shown below. These pins

should not be changed while the H8S/2633 Group is

operating.

MD2 MD1 MD0 Operating Mode

0 0 0 —

1 —

1 0 —

1 —

1 0 0 Mode 4

1 Mode 5

1 0 Mode 6

1 Mode 7

System control RES Input Reset input: When this pin is driven low, the chip is

reset.

MRES Input Manual reset: When this pin is driven low, a

transmission is made to manual reset mode.

STBY Input Standby: When this pin is driven low, a transition is

made to hardware standby mode.

BREQ Input Bus request: Used by an external bus master to issue

a bus request to the H8S/2633 Group.

BREQO Output Bus request output: The external bus request signal

used when an internal bus master accesses external

space in the external bus-released state.

BACK Output Bus request acknowledge: Indicates that the bus has

been released to an external bus master.

FWE Input Flash write enable: Pin for flash memory use (in

planning stage).