Datasheet

Section 17 Smart Card Interface
R01UH0166EJ0600 Rev. 6.00 Page 835 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
• Retransfer operation when SCI is in transmit mode
Figure 17.12 illustrates the retransfer operation when the SCI is in transmit mode.
[6] If an error signal is sent back from the receiving end after transmission of one frame is
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next
parity bit is sampled.
[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality
is received.
[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
[9] If an error signal is not sent back from the receiving end, transmission of one frame, including
a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE
bit in SCR is enabled at this time, a TXI interrupt request is generated.
If data transfer by the DMAC
*
and DTC
*
by means of the TXI source is enabled, the next data
can be written to TDR automatically. When data is written to TDR by the DMAC
*
or DTC
*
,
the TDRE bit is automatically cleared to 0.
Note: * DMAC and DTC functions are not available in the H8S/2695.
D0D1 D2D3 D4D5 D6D7 Dp DE Ds D0 D1D2 D3D4 D5D6 D7Dp
(DE)
Ds
D0 D1 D2 D3 D4Ds
Transfer
frame n+1
Retransferred framenth transfer frame
TDRE
TEND
[6]
FER/ERS
Transfer to TSR from TDR
[7] [9]
[8]
Transfer to TSR from TDR
Transfer to TSR
from TDR
Figure 17.12 Retransfer Operation in SCI Transmit Mode