Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 846 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
SAR
Bit 0
SARX
Bit 0
FS FSX Operating Mode
0 0 I
2
C bus format
• SAR and SARX slave addresses recognized
1 I
2
C bus format (Initial value)
• SAR slave address recognized
• SARX slave address ignored
1 0 I
2
C bus format
• SAR slave address ignored
• SARX slave address recognized
1 Synchronous serial format
• SAR and SARX slave addresses ignored
18.2.3 Second Slave Address Register (SARX)
Bit :
Initial value :
R/W :
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to
SVAX0, differing from the addresses of other slave devices connected to the I
2
C bus.
Bit 0—Format Select X (FSX): Used together with the FS bit in SAR to select the
communication format.
• I
2
C bus format: addressing format with acknowledge bit
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only