Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 850 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 7—I
2
C Bus Interface Enable (ICE): Selects whether or not the I
2
C bus interface is to be
used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer
operations are enabled. When ICE is cleared to 0, the I
2
C bus interface module is halted and its
internal states are cleared.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can
be accessed when ICE is 1.
Bit 7
ICE Description
0 I
2
C bus interface module disabled, with SCL and SDA signal pins
set to port function (Initial value)
I
2
C bus interface module internal states initialized
SAR and SARX can be accessed
1 I
2
C bus interface module enabled for transfer operations (pins SCL and SCA are
driving the bus)
ICMR and ICDR can be accessed
Bit 6—I
2
C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I
2
C
bus interface to the CPU.
Bit 6
IEIC Description
0 Interrupts disabled (Initial value)
1 Interrupts enabled