Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 854 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 1—I
2
C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I
2
C bus interface has
issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave
address or general call address is detected in slave receive mode, when bus arbitration is lost in
master transmit mode, and when a stop condition is detected. IRIC is set at different times
depending on the FS bit in SAR and the WAIT bit in ICMR. See section 18.3.7, IRIC Setting
Timing and SCL Control. The conditions under which IRIC is set also differ depending on the
setting of the ACKE bit in ICCR.
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.
When the DTC
*
is used, IRIC is cleared automatically and transfer can be performed continuously
without CPU intervention.
Note: * The DTC function is not available in the H8S/2695.