Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 858 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
18.2.6 I
2
C Bus Status Register (ICSR)
Bit :
Initial value :
R/W :
Note: * Only 0 can be written, for flag clearing.
7
ESTP
0
R/(W)*
6
STOP
0
R/(W)*
5
IRTR
0
R/(W)*
4
AASX
0
R/(W)*
3
AL
0
R/(W)*
0
ACKB
0
R/W
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge
confirmation and control.
ICSR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been
detected during frame transfer in I
2
C bus format slave mode.
Bit 7
ESTP Description
0 No error stop condition (Initial value)
[Clearing conditions]
1. When 0 is written in ESTP after reading ESTP = 1
2. When the IRIC flag is cleared to 0
1
• In I
2
C bus format slave mode
Error stop condition detected
[Setting condition]
When a stop condition is detected during frame transfer
• In other modes
No meaning
Bit 6—Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been
detected after completion of frame transfer in I
2
C bus format slave mode.