Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 863 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
18.2.7 Serial Control Register X (SCRX)
Bit :
Initial value :
R/W :
7
—
0
R/W
6
IICX1
0
R/W
5
IICX0
0
R/W
4
IICE
0
R/W
3
FLSHE
0
R/W
0
—
0
R/W
2
—
0
R/W
1
—
0
R/W
SCRX is an 8-bit readable/writable register that controls register access, the I
2
C interface operating
mode (when the on-chip IIC option is included), and on-chip flash memory control (F-ZTAT
versions). If a module controlled by SCRX is not used, do not write 1 to the corresponding bit.
SCRX is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Reserved: Do not set 1.
Bits 6 and 5—I
2
C Transfer Select 1 and 0 (IICX1 and IICX0): These bits, together with bits
CKS2 to CKS0 in ICMR of IIC1 and IIC0, select the transfer rate in master mode. For details, see
section 18.2.4, I
2
C Bus Mode Register (ICMR).
Bit 4—I
2
C Master Enable (IICE): Controls CPU access to the I
2
C bus interface data and control
registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR).
Bit 4
IICE Description
0 CPU access to I
2
C bus interface data and control registers is disabled (Initial value)
1 CPU access to I
2
C bus interface data and control registers is enabled
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls the operation of the flash
memory in F-ZTAT versions. For details, see section 22, ROM.
Bits 2 to 0—Reserved: Do not set 1.