Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 864 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
18.2.8 DDC Switch Register (DDCSWR)
Bit :
Initial value :
R/W :
Notes: 1. Should always be written with 0.
2. Always read as 1.
7
—
0
R/(W)*
1
6
—
0
R/(W)*
1
5
—
0
R/(W)*
1
4
—
0
R/(W)*
1
3
CLR3
1
W*
2
0
CLR0
1
W*
2
2
CLR2
1
W*
2
1
CLR1
1
W*
2
DDCSWR is an 8-bit readable/writable register that is used to initialize the IIC module.
DDCSWR is initialized to H'0F by a reset and in hardware standby mode.
Bits 7 to 4—Reserved: Should always be written with 0.
Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal
state of IIC0 and IIC1.
These bits can only be written to; if read they will always return a value of 1.
When a write operation is performed on these bits, a clear signal is generated for the internal latch
circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized.
The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction
such as BCLR.
When clearing is required again, all the bits must be written to in accordance with the setting.
Bit 3 Bit 2 Bit 1 Bit 0
CLR3 CLR2 CLR1 CLR0 Description
0 0 — — Setting prohibited
1 0 0 Setting prohibited
1 IIC0 internal latch cleared
1 0 IIC1 internal latch cleared
1 IIC0 and IIC1 internal latches cleared
1 — — — Invalid setting