Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 867 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
S DATA DATA P
11
n8
1 m
FS = 1 and FSX = 1
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
Figure 18.4 I
2
C Bus Data Format (Serial Format)
SDA
SCL
S
1-7
SLA
8
R/W
9
A
1-7
DATA
89 1-7 89
A DATA PA/A
Figure 18.5 I
2
C Bus Timing
Table 18.4 I
2
C Bus Data Format Symbols
Legend
S Start condition. The master device drives SDA from high to low while SCL is high
SLA Slave address, by which the master device selects a slave device
R/W Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
A Acknowledge. The receiving device (the slave in master transmit mode, or the master
in master receive mode) drives SDA low to acknowledge a transfer
DATA Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or
LSB-first format is selected by bit MLS in ICMR
P Stop condition. The master device drives SDA from low to high while SCL is high