Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 868 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
18.3.2 Initial Setting
At startup the following procedure is used to initialize the IIC.
Clear module stop.
Start initialization
Set IICE = 1 (STCR)
Set DDCSWR
Set ICE = 0 (ICCR)
Set SAR and SARX
Set ICE = 1 (ICCR)
Set ICSR
Set STCR
Set IMCR
Set ICCR
Set MSTP4 = 0 (IIC0)
MSTP3 = 0 (IIC1)
(MSTPCRL)
Enable CPU access by IIC control register and data register.
Clear IIC internal latch
Enable SAR and SARX access.
Set transfer format for 1st slave address, 2nd slave address,
and IIC (SVA8–SVA0, FS, SVAX6–SVAX0, FSX).
Enable IMCR and IMDR access. Use SCL and SDA pins is IIC
port.
Set acknowledge bit (ACKB).
Set transfer rate (IICX).
Set transfer format, wait insertion, and transfer rate (MLS,
WAIT, CKS2–CKS0).
Set interrupt enable, transfer mode, and acknowledge
judgment (IEIC, MST, TRS, ACKE).
Transmit/receive start
Figure 18.6 Flowchart for IIC Initialization (Example)
Note: The ICMR register should be written to only after transmit or receive operations have
completed. Writing to the ICMR register while a transmit or receive operation is in
progress could cause an erroneous value to be written to bit counter bits BC2 to BC0. This
could result in improper operation.
18.3.3 Master Transmit Operation
In I
2
C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
Figure 18.7 is a flowchart showing an example of the master transmit mode.