Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 869 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Start
Initial settings
Write BBSY = 1
and SCP = 0 (ICCR)
BBSY = 0?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
[1] Initial settings.
[2] Determine status of SCL and SDA lines.
[3] Set to master transmit mode.
[4] Generate start condition.
[5] Wait for start condition to be met.
[6] Set 1st byte (slave address + R/W) transmit data.
(Perform ICDR write and IRIC flag clear
operations continuously.)
[7] Wait for end of 1 byte transmission.
[8] Judge acknowledge signal from specified.
slave device.
[9] Set transmit data for 2nd byte onward.
(Perform ICDR write and IRIC flag clear
operations continuously.)
[10] Wait for end of 1 byte transmission.
[11] Judge end of transmission.
[12] Generate stop condition.
Set MST = 1
and TRS = 1 (ICCR)
Read IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Write transmit data to ICDR
Read BBSY flag in ICCR
Read ACKB bit in ICSR
IRIC = 1?
No
No
No
IRIC = 1?
Transmit mode?
ACKB = 0?
Clear IRIC flag in ICCR
Write transmit data to ICDR
Read IRIC flag in ICCR
Read ACKB bit in ICSR
Clear IRIC flag in ICCR
Transmit complete?
(ACKB = 1?)
No
IRIC = 1?
Write BBSY = 0 and
SCP = 0 (ICCR)
End
Master receive mode
Figure 18.7 Flowchart for Master Transmit Mode (Example)