Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 871 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
[11] Read the ACKB bit in ICSR to confirm that the slave device has returned an acknowledge
signal and the value of ACKB is 0. If the slave device has not returned an acknowledge signal
and the value of ACKB is 1, perform the transmit end processing described in step [12].
[12] Clear the IRIC flag to 0. Write 0 to the ACKE bit in ICCR and clear the received ACKB bit to
0.
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and
generates the stop condition.
1
[5]
R/W
[7]
A
23456789 12
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6
Data 1
Data 1
Data 1
Slave address
Generate start
condition
Interrupt
request
Interrupt
request
Address + R/W
Address + R/W
[9] IRIC clearance[9] ICDR write[6] IRIC clearance[6] ICDR write[4] Write BBSY = 1
and SCP = 0
(generate start
condition)
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
ICDRE
IRIC
IRTR
ICDRT
ICDRS
User processing
Improper operation will
result.
Note: ICDR data
setting timing
Normal operation
Figure 18.8 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0)