Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 872 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
[7]
[10]
AA
123456789
Generate start
condition
89
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
ICDRE
IRIC
IRTR
ICDR
Bit 7Bit 0 Bit 6
Data 2
Data 2Data 1
Data 1
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[12] Write BBSY = 0
and SCP = 0
(generate stop
condition)
[12] IRIC clearance
[11] ACKB read[9] IRIC clearance[9] ICDR write
User processing
Figure 18.9 Example of Master Transmit Mode Stop Condition Generation Timing
(MLS = WAIT = 0)
18.3.4 Master Receive Operation
In I
2
C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data.
The master device transmits the data containing the slave address + R/W (0: read) in the 1st frame
after a start condition is generated in the master transmit mode. After the slave device is selected
the switch to receive operation takes place.
(1) Receive Operation Using Wait States
Figures 18.10 and 18.11 are flowcharts showing examples of the master receive mode (WAIT =
1).