Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 874 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Set WAIT = 1 (ICMR)
Clear IRIC flag in ICCR
Set ACKB = 0 (ICSR)
Set TRS = 0 (ICCR)
Read ICDR
Read IRIC flag in ICCR
IRIC = 1?
No
Yes
Yes
No
[1] Set to receive mode
[2] Receive start, dummy read.
[7] Set acknowledge data for final receive.
[9] Set TRS to generate stop condition.
[11] Clear IRIC flag (cancel wait state).
[16] Read final receive data.
[15] Cancel wait mode
Clear IRIC flag. (IRIC flag should be
cleared when WAIT = 0.)
[17] Generate stop condition.
[12] Wait for end of reception of 1 byte.
(IRIC set at rising edge of 9th clock cycle)
Clear IRIC flag in ICCR
Set ACKB = 1 (ICSR)
Set TRS = 1 (ICCR)
Read IRIC flag in ICCR
Set WAIT = 0 (ICMR)
Clear IRIC flag in ICCR
Read ICDR
IRIC = 1?
Write BBSY = 0
and SCP = 0 (ICCR)
End
Master receive mode
[3] Receive wait state (IRIC set at falling edge
of 8th clock cycle) or
Wait for end of reception of 1 byte
(IRIC set at rising edge of 9th clock cycle).
Figure 18.11 Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1)
(Example)
The procedure for receiving data sequentially, using the wait states (WAIT bit) for
synchronization with ICDR (ICDRR) read operations, is described below.
The procedure below describes the operation for receiving multiple bytes. Note that some of the
steps are omitted when receiving only 1 byte. Refer to figure 18.11 for details.