Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 877 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
19
A
2345 12345678 9
Data 1
Data 1
Master receive modeMaster transmit mode
Data 2
[3]
[3]
A
[4] IRTR = 1[4] IRTR = 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3Bit 2 Bit 1 Bit 0
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing
[1] TRS cleared to 0
IRIC clearance
[2] ICDR read (dummy read)
[6] IRIC clearance
(cancel wait)
[5] ICDR read
(data 1)
[6] IRIC clearance
Figure 18.12 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
9821345678 9
A
A
Data 2 Data 3
Data 3Data 2Data 1
[3]
[3]
[8]
[12] [12]
Stop condition
generated
[4] IRTR = 0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Bit 0
1 clock cycle wait time
Bit 7
[4] IRTR = 1 [13] IRTR = 1[13] IRTR = 0
[15] WAIT cleared to 0
IRIC clearance
[14] IRIC clearance
[11] IRIC clearance
[6] IRIC clearance
User processing
[10] ICDR read (data 2)
[16] ICDR read (data 3)
[9] TRS set to 1
[7] ACKB set to 1
SCL
(master output)
SDA
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
[17] Stop condition
issued
Figure 18.13 Example of Master Receive Mode Stop Condition Generation Timing
(MLS = ACKB = 0, WAIT = 1)