Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 890 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0.
2. Clear of bits BC2 to BC0.
3. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBST bit
to 0, and wait for two transfer rate clock cycles.
4. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0.
5. Initialize (re-set) the IIC registers.
18.4 Usage Notes
• In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
• Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
⎯ Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
⎯ Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
• Table 18.6 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.