Datasheet
Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 893 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Table 18.8 I
2
C Bus Timing (with Maximum Influence of t
Sr
/t
Sf
)
Time Indication (at Maximum Transfer Rate) [ns]
Item
t
cyc
Indication
t
Sr
/t
Sf
Influence
(Max.)
I
2
C Bus
Specifi-
cation
(Min.)
φ =
5 MHz
φ =
8 MHz
φ =
10 MHz
φ =
16 MHz
φ =
20 MHz
φ =
25 MHz
φ =
28 MHz
t
SCLHO
0.5 t
SCLO
(–t
Sr
)
Standard
mode
–1000 4000 4000 4000 4000 4000 4000 4000 4000
High-speed
mode
–300 600 950 950 950 950 950 950 950
t
SCLLO
0.5 t
SCLO
(–t
Sf
)
Standard
mode
–250 4700 4750 4750 4750 4750 4750 4750 4750
High-speed
mode
–250 1300 1000
*
1
1000
*
1
1000
*
1
1000
*
1
1000
*
1
1000
*
1
1000
*
1
t
BUFO
0.5 t
SCLO
–
1 t
cyc
( –t
Sr
)
Standard
mode
–1000 4700 3800
*
1
3875
*
1
3900
*
1
3938
*
1
3950
*
1
3960
*
1
3964
*
1
High-speed
mode
–300 1300 750
*
1
825
*
1
850
*
1
888
*
1
900
*
1
910
*
1
912
*
1
t
STAHO
0.5 t
SCLO
–
1 t
cyc
(–t
Sf
)
Standard
mode
–250 4000 4550 4625 4650 4688 4700 4710 4713
High-speed
mode
–250 600 800 875 900 938 950 960 964
t
STASO
1 t
SCLO
(–t
Sr
)
Standard
mode
–1000 4700 9000 9000 9000 9000 9000 9000 9000
High-speed
mode
–300 600 2200 2200 2200 2200 2200 2200 2200
t
STOSO
0.5 t
SCLO
+ 2 t
cyc
(–t
Sr
)
Standard
mode
–1000 4000 4400 4250 4200 4125 4100 4080 4071
High-speed
mode
–300 600 1350 1200 1150 1075 1050 1030 1021
t
SDASO
(master)
1 t
SCLLO
*
3
–
3 t
cyc
(–t
Sr
)
Standard
mode
–1000 250 3100 3325 3400 3513 3550 3580 3593
High-speed
mode
–300 100 400 625 700 813 850 880 893
t
SDASO
(slave)
1 t
SCLL
*
3
–
12 t
cyc
*
2
(–t
Sr
)
Standard
mode
–1000 250 3100 3325 3400 3513 3550 3580 3593
High-speed
mode
–300 100 400 625 700 813 850 880 893
t
SDAHO
3 t
cyc
Standard
mode
0 0 600 375 300 188 150 120 107
High-speed
mode
0 0 600 375 300 188 150 120 107
Notes: 1. Does not meet the I
2
C bus interface specification. Remedial action such as the following is necessary: (a) secure a
start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive
load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending
on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the I
2
C bus
interface specifications are met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (1t
SCLL
– 6t
cyc
).
3. Calculated using the I
2
C bus specification values (standard mode: 4700 ns min.; high-speed mode: 1300 ns min.).