Datasheet

Section 1 Overview
R01UH0166EJ0600 Rev. 6.00 Page 39 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Type Symbol I/O Name and Function
Data bus D15 to D0 I/O Data bus: These pins constitute a bidirectional data
bus.
Bus control CS7 to CS0 Output Chip select: Selection signal for areas 0 to 7.
AS Output Address strobe: When this pin is low, it indicates that
address output on the address bus is enabled.
RD Output Read: When this pin is low, it indicates that the
external address space can be read.
HWR Output High write/write enable/upper write enable:
A strobe signal that writes to external space and
indicates that the upper half (D15 to D8) of the data
bus is enabled.
The 2CAS type DRAM write enable signal.
The 2WE type DRAM upper write enable signal.
LWR Output Low write/lower column address strobe/lower write
enable:
A strobe signal that writes to external space and
indicates that the lower half (D7 to D0) of the data bus
is enabled.
The 2CAS type (LCASS = 1) DRAM lower column
address strobe signal.
The 2WE type DRAM lower write enable signal.
CAS Output Upper column address strobe/column address strobe:
The 2CAS type DRAM upper column address strobe
signal.
LCAS Output Lower column address strobe:
The 2CAS type DRAM lower column address strobe
signal.
OE Output Output enable:
Output enable signal for DRAM space read access.
WAIT Input Wait: Requests insertion of a wait state in the bus
cycle when accessing external 3-state address space.
DMA controller
(DMAC)
DREQ1,
DREQ0
Input DMA request 1,0:
Requests DMAC activation.
TEND1,
TEND0
Output DMA transfer completed 1,0:
Indicates DMAC data transfer end.
DACK1,
DACK0
Output DMA transfer acknowledge 1,0:
DMAC single address transfer acknowledge pin.