Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 898 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
• Notes on ICDR Reads and ICCR Access in Slave Transmit Mode
In a transmit operation in the slave mode of the I
2
C bus interface, do not read the ICDR
register or read or write to the ICCR register during the period indicated by the shaded portion
in figure 18.25.
Normally, when interrupt processing is triggered in synchronization with the rising edge of the
9th clock cycle, the period in question has already elapsed when the transition to interrupt
processing takes place, so there is no problem with reading the ICDR register or reading or
writing to the ICCR register.
To ensure that the interrupt processing is performed properly, one of the following two
conditions should be applied.
(1) Make sure that reading received data from the ICDR register, or reading or writing to the
ICCR register, is completed before the next slave address receive operation starts.
(2) Monitor the BC2–BC0 counter in the ICMR register and, when the value of BC2–BC0 is
000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in order
to involve the problem period in question before reading from the ICDR register, or
reading or writing to the ICCR register.
SDA
R/W
Waveforms if
problem occurs
Bit 7
ICDR write
Data transmission
Period when ICDR reads and ICCR
reads and writes are prohibited
(6 system clock cycles)
Detection of 9th clock
cycle rising edge
A
89
SCL
TRS
Address received
Figure 18.25 ICDR Read and ICCR Access Timing in Slave Transmit Mode