Datasheet

Section 18 I
2
C Bus Interface [Option]
(This function is not available in the H8S/2695)
Page 902 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
• Notes on Wait Operation in Master Mode
During master mode operation using the wait function, when the interrupt flag IRIC bit is
cleared from 1 to 0 between the falling edge of the 7th clock cycle and the falling edge of the
8th clock cycle, in some cases no wait is inserted after the falling edge of the 8th clock cycle
and the clock pulse of the 9th clock cycle is output continuously.
Observe the following with regard to clearing the IRIC flag while using the wait function.
At the rising edge of the 9th clock cycle, set the IRIC flag to 1 and then clear it to zero before
the rising edge of the 1st clock cycle (while the value of the BC2 to BC0 counter value is 2 or
greater).
If clearing of the IRIC flag is delayed by interrupt processing or the like and the BC counter
value reaches 1 or 0, confirm that the SCL pin state is low-level after the BC2 to BC0 counter
has reached 0 and then clear the IRIC flag. (See figure 18.28.)
SCL
BC2 to BC0
Clear IRIC when
BC2 to BC0 ≥ 2.
IRIC flag can be cleared.IRIC flag can be cleared.
IRIC flag cannot be cleared.
9
AA
123 45678 9123
SDA
Transit/receive data Transit/receive data
Confirm SCL pin
is low-level.
Clear IRIC.
IRIC
(operation example)
07654321 765
Figure 18.28 Timing of IRIC Flag Clearing During Wait Operation