Datasheet

Section 19 A/D Converter
Page 906 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
19.1.4 Register Configuration
Table 19.2 summarizes the registers of the A/D converter.
Table 19.2 A/D Converter Registers
Name Abbreviation R/W Initial Value Address
*
1
A/D data register AH ADDRAH R H'00 H'FF90
A/D data register AL ADDRAL R H'00 H'FF91
A/D data register BH ADDRBH R H'00 H'FF92
A/D data register BL ADDRBL R H'00 H'FF93
A/D data register CH ADDRCH R H'00 H'FF94
A/D data register CL ADDRCL R H'00 H'FF95
A/D data register DH ADDRDH R H'00 H'FF96
A/D data register DL ADDRDL R H'00 H'FF97
A/D control/status register ADCSR R/(W)
*
2
H'00 H'FF98
A/D control register ADCR R/W H'33 H'FF99
Module stop control register A MSTPCRA R/W H'3F H'FDE8
Notes: 1. Lower 16 bits of the address.
2. Bit 7 can only be written with 0 for flag clearing.