Datasheet

Section 19 A/D Converter
Page 908 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
19.2.2 A/D Control/Status Register (ADCSR)
7
ADF
0
R/(W)*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CH3
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
Bit
Initial value
R/W
:
:
:
Note: * Only 0 can be written to bit 7, to clear this flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations.
ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode.
Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7
ADF Description
0 [Clearing conditions] (Initial value)
• When 0 is written to the ADF flag after reading ADF = 1
• When the DMAC
*
or DTC
*
is activated by an ADI interrupt and ADDR is read
1 [Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
Note: * The DMAC and DTC functions are not available in the H8S/2695.
Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests
at the end of A/D conversion.
Bit 6
ADIE Description
0 A/D conversion end interrupt (ADI) request disabled (Initial value)
1 A/D conversion end interrupt (ADI) request enabled