Datasheet

Section 19 A/D Converter
R01UH0166EJ0600 Rev. 6.00 Page 911 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
19.2.3 A/D Control Register (ADCR)
7
TRGS1
0
R/W
6
TRGS0
0
R/W
5
—
1
—
4
—
1
—
3
CKS1
0
R/W
0
—
1
—
2
CKS0
0
R/W
1
—
1
—
Bit
Initial value
R/W
:
:
:
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion operations and sets the A/D conversion time.
ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode.
Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of
the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion
is stopped (ADST = 0).
Bit 7 Bit 6
TRGS1 TRGS0 Description
0 0 A/D conversion start by software is enabled (Initial value)
1 A/D conversion start by TPU conversion start trigger is enabled
1 0 A/D conversion start by 8-bit timer
*
conversion start trigger is enabled
1 A/D conversion start by external trigger pin (ADTRG) is enabled
Note: * This function is not available in the H8S/2695.
Bits 5, 4, 1, and 0—Reserved: They are always read as 1 and cannot be modified.
Bits 3 and 2—Clock Select 1 and 0 (CKS1, CKS0): These bits select the A/D conversion time.
The conversion time should be changed only when ADST = 0.
Set bits CKS1 and CKS0 to give a conversion time of at least 10 µs when AV
CC
≥ 4.5 V, and at
least 16 µs when AV
CC
< 4.5 V.
Bit 3 Bit 2
CKS1 CKS0 Description
0 0 Conversion time = 530 states (max.) (Initial value)
1 Conversion time = 266 states (max.)
1 0 Conversion time = 134 states (max.)
1 Conversion time = 68 states (max.)