Datasheet

Section 19 A/D Converter
Page 918 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
19.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t
D
after the ADST bit is set to 1, then starts conversion. Figure 19.5 shows the A/D
conversion timing. Table 19.4 indicates the A/D conversion time.
As indicated in figure 19.5, the A/D conversion time includes t
D
and the input sampling time. The
length of t
D
varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 19.4.
In scan mode, the values given in table 19.4 apply to the first conversion time. The values given
in table 19.5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and
CKS0 in ADCR to give a conversion time of at least 10 µs when AV
CC
≥ 4.5 V, and at least 16 µs
when AV
CC
< 4.5 V.
(1)
(2)
t
D
t
SPL
t
CONV
φ
Input sampling
timing
ADF
Address
Write signal
Legend:
(1): ADCSR write cycle
(2): ADCSR address
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 19.5 A/D Conversion Timing