Datasheet

Section 21 RAM
Page 936 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
21.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 21.1 shows the address and initial value of
SYSCR.
Table 21.1 RAM Register
Name Abbreviation R/W Initial Value Address
*
System control register SYSCR R/W H'01 H'FDE5
Note: * Lower 16 bits of the address.
21.2 Register Descriptions
21.2.1 System Control Register (SYSCR)
7
MACS
0
R/W
6
—
0
—
5
INTM1
0
R/W
4
INTM0
0
R/W
3
NMIEG
0
R/W
0
RAME
1
R/W
2
MRESE
0
R/W
1
—
0
—
Bit
Initial value
R/W
:
:
:
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Note: When the DTC is used, the RAME bit must not be cleared to 0.
(The DTC function is not available in the H8S/2695.)
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)