Datasheet

Section 22 ROM
Page 940 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Table 22.1 Register Configuration
Register Name Abbreviation R/W Initial Value Address
*
Mode control register MDCR R/W Undefined H'FDE7
Note: * Lower 16 bits of the address.
22.2 Register Descriptions
22.2.1 Mode Control Register (MDCR)
Bit: 7 6 5 4 3 2 1 0
— — — — — MDS2 MDS1 MDS0
Initial value: 1 0 0 0 0 —
*
—
*
—
*
R/W: R/W — — — — R R R
Note: * Determined by pins MD2 to MD0.
MDCR is an 8-bit read-only register used to monitor the current H8/2633 Group operating mode.
Bit 7—Reserved: Only 1 should be written to this bit.
Bits 6 to 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to
MD0. MDS2 to MDS0 are read-only bits, and cannot be modified. The mode pin (MD2 to MD0)
input levels are latched into these bits when MDCR is read. These latches are canceled by a
power-on reset, but are retained in a manual reset.
22.3 Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can
be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to
the lower 8 bits. Word data must start at an even address.
The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0).
These settings are shown in table 22.2.